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Infineon introduces next-generation OptiMOS

A multiple-time programming (MTP) memory allows customisation during design and high-volume manufacturing, significantly reducing design cycles and time-to-market.

Infineon Technologies AG introduced a new family of OptiMOS 5 IPOL buck regulators with VR14-compliant SVID standard and I2C/PMBus digital interfaces for Intel/AMD server CPUs and network ASICs/FPGAs. Housed in a 5 x 6 mm2 PQFN package, these devices are an easy-to-use, fully integrated, and highly efficient solution for next-generation server, storage, telecom, and datacom applications, as well as distributed power systems.

The OptiMOS IPOL single-voltage synchronous buck regulator TDA38640 supports up to 40 A output current. The device comes with Intel SVID and I2C/PMBus digital interfaces and can be used for Intel VR12, VR12.5, VR13, VR14, IMPVP8 designs, and DDR memory without significant changes to the bill of materials (BOM). Infineon’s TDA38740 and TDA38725 digital IPOL buck regulators support up to 40 A and 25 A output current, respectively, and come with a PMBus interface. All three new devices use Infineon’s proprietary fast constant on time (COT) PWM engine to deliver industry-leading transient performance while simplifying the design development.

The onboard PWM controller and OptiMOS FETs with integrated bootstrap diode make these new devices a small footprint solution with highly-efficient power delivery. In addition, they provide the required versatility by operating in a broad input and output voltage range while offering programmable switching frequencies from 400 kHz to 2 MHz. A multiple-time programming (MTP) memory allows customization during design and high-volume manufacturing, significantly reducing design cycles and time-to-market. They also offer a digitally programmable load line that can be set via configuration registers without external components, resulting in a simplified BOM. The device configuration can be easily defined using Infineon’s XDP Designer GUI and is stored in the on-chip memory.

As artificial intelligence (AI) technology is integrated into massive data centers, the demand for higher performance will continue to increase. Following this trend, high power density and energy-efficient solutions for smart enterprise systems have also become challenging.