Siemens Digital Industries Software has recently unveiled its next-generation Veloce™ hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs. The company said this is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.
New products in the Veloce hardware-assisted verification system are:
– Veloce HYCON (HYbrid CONfigurable) for virtual platform/software-enabled verification. Veloce HYCON delivers innovative technology that allows customers to engineer and deploy complex hybrid emulation systems for their next-generation system-on-chip (SoC) designs.
– Veloce Strato+, a capacity upgrade to the Veloce Strato hardware emulator. With an industry-leading capacity roadmap that scales up to 15 billion gates, Veloce Strato+ combines the industry’s highest total throughput with its fastest co-model bandwidth and time-to-visibility.
– Veloce Primo for enterprise-level FPGA prototyping, an internally developed enterprise prototyping solution that combines industry-leading runtime performance with exceptionally fast prototype bring-up.
– Veloce proFPGA for desktop FPGA prototyping. With a modular approach to capacity, the Veloce proFPGA family of products delivers scalability across a range of capacity requirements.
The company said this highly cohesive system sets a new standard for the future direction of hardware-assisted verification methodologies. “The system takes hardware, software and system verification to the next level of intelligent digitalization by streamlining and optimizing verification cycles while helping to reduce verification cost,” it said.
This seamless approach to managing verification cycles emphasizes running market-specific, real-world workloads, frameworks, and benchmarks early in the verification cycle for power and performance analysis. This enables customer-built virtual SoC models early in the cycle and the integration to begin running real-world firmware and software on Veloce Strato+ for deep-visibility to the lowest level of hardware.
Customers can then move the same design to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. To make this approach as efficient as possible, Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content. This is a necessary foundation for a seamless methodology.
“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, Senior Vice President and General Manager, Siemens EDA.
“The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade.”
With today’s announcement, he said they are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.
The full Veloce Hardware-Assisted Verification system is now available and in production use at leading customers worldwide.